MPhil in Electronic & Comp Engg - A Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic

Name: MPhil in Electronic & Comp Engg - A Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic
Start: 2021-08-02
End: 2021-08-02

2021 年 8 月 2 日

2:00pm - 5:00pm