MPhil in Electronic & Comp Engg - A Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic

Name: MPhil in Electronic & Comp Engg - A Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic
Start: 2021-08-02
End: 2021-08-02

2021 年 8 月 2 日

2:00pm - 5:00pm

, HKUST

Supporting the below United Nations Sustainable Development Goals:支持以下聯合國可持續發展目標：支持以下联合国可持续发展目标：

活动形式

论文答辩

候选人

WONG, Yuk

语言

英文