SRAM Design: The Basics
Static Random Access Memory (SRAM) constitutes the cornerstone of data storage in modern System-on-chip architectures and mainstream mobile as well as server-class microprocessors. SRAM is used for the implementation of various levels of cache hierarchy as well as internal registers of the microprocessor. The standard 6-Transistor SRAM bitcell design is a careful trade-off between three metrics: data retention, read stability, and write-ability. The constant demand for dense memory arrays, coupled with technology and voltage scaling have reduced the safety margins associated with these performance metrics. In this talk, the basics of SRAM bitcell topology will be covered together with details and trade-offs associated with bitcell read and write operation.
Khawar Sarfraz (S’07–M’10) received his B.Sc. degree in Electronic Engineering from GIK Institute of Engineering Sciences and Technology, Topi, Pakistan, in 2000, the M.Sc. degree in Electrical Engineering (Specialization: Microelectronics) from Delft University of Technology, Delft, The Netherlands, in 2009, and the Ph.D. degree in Electronic and Computer Engineering from The Hong Kong University of Science and Technology, Hong Kong, in 2016. He is the author/co-author of 4 journal articles and 13 conference publications.
He has been associated with the semiconductor industry for over 11 years in Europe, Pakistan, and Hong Kong. During this time, he was involved in the design, verification, and project management for telecom test equipment, radar sub-systems for the aerospace industry, embedded memory design for media processors, and SerDes IP development for the datacenter segment. In addition, he has served as regular and visiting faculty for over 2 years at Lahore University of Management Sciences (LUMS), Lahore, Pakistan, and at the Center for Advanced Studies in Engineering (CASE), Islamabad, Pakistan, where he was responsible for teaching UG/PG courses in Electrical Engineering, supervision of a Master Thesis, curriculum co-development, and administrative duties.