Public Research Seminar by Microelectronics Thrust, Function Hub, HKUST (GZ) - Software & Hardware Codesign of CIM Accelerator for Deep Learning Algorithm
The machine/deep learning algorithms typically require enormous computational and memory resources to train the model parameters and/or the inference, which imposes a "memory wall" problem to the computing system. Therefore, a radical shift of the computing paradigm towards "compute-in-memory (CIM)" is an attractive solution, where logic and memory array are integrated, and the data-intensive computation is offloaded to the memory periphery. However, CIM behaves differently from traditional digital circuits, requiring more cross-layer designs from algorithm levels to hardware implementations. As a penalty, new challenges such as ADC offset, process variation, and device nonidealities will be generated, limiting the algorithm's performance from inference to training. Our study focuses on the software/hardware codesign methodologies to these challenges in CIM design.
Shanshi Huang (Graduate Student Member, IEEE) received the B.S. degree in communication engineering from Beijing Institute of Technology, Beijing, China, in 2012, and the M.S. degree in electrical engineering from Arizona State University, Tempe, AZ, USA, in 2014. She is pursuing her Ph.D. degree in electrical and computer engineering with the Georgia Institute of Technology, Atlanta, GA, USA. Her current research interests include deep learning algorithms & hardware codesign, and deep learning security.