Examination Committee

Prof Chi Ying TSUI, ECE/HKUST (Chairperson)
Prof Wei ZHANG, ECE/HKUST (Thesis Supervisor)
Prof Chin-Tau LEA, ECE/HKUST

Abstract

As chip-multiprocessors are gaining great prominence in computing systems, we are witnessing a shift in focus from computation to communication. The interconnection network between processors and memory defines the memory latency and memory bandwidth, which now have greater bearing on the system performance than the compute power of processors themselves. Providing efficient communication infrastructure between multiple computing cores and the on-chip memory is an important consideration. Network on chip (NoC) has emerged as a scalable, compact and manageable on-chip interconnect solution for future chip multiprocessors. Performance analysis is an integral step of the NoC design flow. We present an extended framework for worst-case throughput analysis of network on chip interconnects. It is a step up from the conventional analytical models for NoCs which only consider channel/link activity as the basis of analysis. In our model, we include the router constraints which lead to a more accurate modelling of NoC performance. We compare our model against the traditional approach and found that our model is closer to the performance evaluations obtained from simulations. We believe that this will significantly improve the NoC design space exploration and provide a more comprehensive approach to performance evaluation of NoCs. Secondly, we address the major performance bottleneck in heterogeneous chip multiprocessors, namely, the memory bandwidth between the on-chip system and off-chip memory. We use multi-criteria optimization for efficient memory controller placement schemes to optimize off-chip memory access for general heterogeneous applications and extend it for domain-specific applications. Experimental results demonstrate that our method can accelerate such applications by improving the average network latency and link utilization with minimal change to network components over existing schemes.