Integration of Low Loss Interconnects in CMOS
2pm
Room 2302 (Lifts 17-18), 2/F Academic Building, HKUST

Supporting the below United Nations Sustainable Development Goals:支持以下聯合國可持續發展目標:支持以下联合国可持续发展目标:

Examination Committee

Prof Zhigang LI, MAE/HKUST (Chairperson)
Prof Man Sun CHAN, ECE/HKUST (Thesis Supervisor)
Prof Patrick YUE, ECE/HKUST (Thesis Co-supervisor)
Prof H.-S. Philip WONG, Department of Electrical Engineering, Stanford University (External Examiner)
Prof Wing Hung KI, ECE/HKUST
Prof Kevin J CHEN, ECE/HKUST
Prof Zhi Yu YANG, PHYS/HKUST

 

Abstract

In this work, an interlayer dielectric with an extremely low dielectric constant of 1.96 is achieved using SiO2 with vertically aligned cylindrical pores. Vertically grown carbon nanotubes are used as templates to form cylindrical pores to achieve high porosity while maintaining structural stability. Measurements show that an elastic modulus of 17.5 GPa can be maintained, even at 65% porosity, to provide sufficient mechanical strength for most back end of line (BEOL) processes. The tradeoff between the dielectric constant and elastic modulus for different porous structures has also been studied to project the ultimate achievable k-value.

A BEOL compatible thick dielectric and metal-based interconnect, which eliminates the resistive and substrate eddy current loss from on-chip magnetics, is also proposed. Fully integrated on-chip inductors with up to 200 nH/mm2 inductance density and a peak quality factor of 25, have been implemented based on the proposed interconnect technology, and a complete system for an on-chip wireless power supply has been implemented to demonstrate the integration capability. A 2.5 × 2.5 mm2 wireless power receiver chip can harvest 27 mW power from a 250 mW transmitting power source at a distance of 5.3 mm, which is the best power harvesting capability compared to that of other reported technologies.

The thick dielectric interconnect technology is also proved to be useful to minimize the radiation loss of on-chip antennas. Several millimeter-wave antenna topologies are demonstrated utilizing this technology. An on-chip triangular sleeve monopole, which has a wide bandwidth from 23 GHz to 63 GHz, with 3.5 dB gain and efficiency of 98%, has been implemented. The antenna is integrated with a foundry fabricated wideband power amplifier IC. This demonstrates the efficacy of the proposed interconnect technology, which has applications ranging from power management to high-speed wireless data communication.

講者/ 表演者:
Mr Salahuddin RAJU
語言
英文