Examination Committee

Prof Shiheng WANG, ACCT/HKUST (Chairperson)
Prof Patrick YUE, ECE/HKUST (Thesis Supervisor)
Prof Quan XUE, Department of Electronic Engineering, City University of Hong Kong (External Examiner)
Prof Kevin J CHEN, ECE/HKUST
Prof Wing Hung KI, ECE/HKUST
Prof Lilong CAI, MAE/HKUST

Abstract

The growing deployment of bandwidth-intensive multimedia applications and cloud computing continue to escalate the burden on today’s communication network. Meanwhile, the demand for high-performance data traffic has gradually migrated from centralized telecommunication infrastructures to cost-sensitive mobile applications and consumer electronics. Therefore, the need for cost reduction of peripheral devices in mobile networks are accelerating. A hybrid fiber-wireless network is a promising approach to provide a flexible and high performance solution for short-range (< 1 km) backhaul links deployment in high data traffic areas. Such systems will require the integration of optical and wireless communication transceiver circuits. To address this emerging trend, this thesis presents the design and implementation of optical-to-millimeter-wave (mmW) modulator system-on-a-chip (SoC) using mainstream CMOS technology for supporting low-cost deployment of such network.
 
In this thesis, an optical-to-mmW modulator SoC with a fully integrated 850-nm wavelength optical receiver front-end and a 60-GHz QPSK modulator is presented for the first time. An inverter-based TIA with a multiple-peaking network is proposed to address design challenges of conventional CMOS TIAs. The peaking network effective extends the TIA bandwidth by 2.8 times. A power efficiency of 0.12 pJ/bit is achieved by the optimized inverter based core amplifier. Realized in 65-nm CMOS, the overall optical receiver front-end achieves-3-dBm input sensitivity at 4 Gb/s with 10-12 BER. The quadrature modulator directly up-converts the de-multiplexed 2-Gb/s I&Q NRZ data to a 4-Gb/s QPSK signal at 60-GHz mmW band. Our design demonstrates that a small form factor and low-cost optical-to-mmW modulator can be realized in mainstream CMOS technology to support cost-effective implementation of fiber-wireless networks. A clock and data recovery (CDR) unit is required following the optical receiver front-end for generating a phase-aligned clock to de-serialize the high-speed incoming data. In this thesis, a power-efficient CDR with embedded equalization to achieve error free operation up to 26 Gb/s under 13-dB channel loss has been developed. The proposed CDR can be further integrated with the fiber-wireless modulator to realize a more complete fiber-wireless SoC.