ECE Seminar - Development of high-performance p-type oxide and halide transistors
Keywords : Oxide Semiconductor, Tellurium oxide, Halide perovskite, pMOS, thin film transistor, hole mobility
Developing high-mobility p-type oxide semiconductors that can be grown using silicon-compatible processes at low temperatures, has remained challenging in the electronics community to integrate complementary electronics with the well-developed n-type counterparts. This presentation will discuss our recent progress in developing high-performance p-type semiconductors as channel materials for thin film transistors. For the first part of my talk, I present an amorphous p-type oxide semiconductor composed of selenium-alloyed tellurium in a tellurium sub-oxide matrix, demonstrating its utility in high-performance, stable p-channel TFTs, and complementary circuits [1]. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of ~15 cm² V-¹ s-¹ and on/off current ratios of 106~107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient aging.
Tin (Sn²+) halide perovskites emerge as promising p-type candidates but suffer from low crystallisation controllability and high film defect density, which result in uncompetitive device performance. In the second part of my talk, I would like to introduce a general overview and recent progress of our group of p-type Sn-based metal halide perovskites for applying field-effect transistors (FETs). I will mainly address inorganic perovskite thin-film transistors with exceptional performance using high-crystallinity and uniform cesium-tin-triiodide-based semiconducting layers with moderate hole concentrations and superior Hall mobilities, which are enabled by the judicious engineering of film composition and crystallization. The optimized devices exhibit high field-effect hole mobilities of over 50 cm² V-¹ s-¹, large current modulation greater than 108, and high operational stability and reproducibility [1,2]. Next, I will introduce A-site cation engineering method to achieve high-performance pure-Sn perovskite thin-film transistors (TFTs). We explore triple A-cations of caesium-formamidinium-phenethylammonium to create high-quality cascaded Sn perovskite channel films, especially with low-defect phase-pure perovskite/dielectric interface. As such, the optimized TFTs show record hole mobilities of over 70 cm² V-¹ s-¹ and on/off current ratios of over 108, comparable to the commercial low-temperature polysilicon technique level [3]. The p-channel perovskite TFTs also show high processability and compatibility with the n-type metal oxides, enabling the integration of high-gain complementary inverters and rail-to-rail logic gates.
References
[1] A. Liu, Y.-Y. Noh et al, Nature, 629,?798–802 (2024)
[2] A. Liu, Y.-Y. Noh et al, Nature Electronics 5, 78-83 (2022).
[3] A. Liu Y.-Y. Noh et al, Nature Electronics 6, 559-571 (2023).
[4] H. H. Zhu, Y.-Y. Noh et al, Nature Electronics 6, 650-657 (2023).
Yong-Young Noh is Chair Professor of the Department of Chemical Engineering of Pohang University of Science and Technology (POSTECH). He received his PhD degree in 2005 from GIST and then worked at the Cavendish Laboratory in Cambridge, UK, as a postdoctoral associate. Afterwards, he worked at ETRI as a senior researcher, as assistant professor at Hanbat National University, and as associate professor at Dongguk University. His research interest is developing novel semiconductors for field-effect transistors, photodetectors, and light-emitting diodes. He is fellow of Korean Academy of Science and Technology and The National Academy of Engineering of Korea.