Examination Committee

Prof Yongsheng GAO, MAE/HKUST (Chairperson)
Prof Mansun CHAN, ECE/HKUST (Thesis Supervisor)
Prof Charles SURYA, Department of Electronic and Information Engineering, The Hong Kong Polytechnic University (External Examiner
Prof Andrew POON, ECE/HKUST
Prof Wei ZHANG, ECE/HKUST
Prof Rolf Walter LORTZ, PHYS/HKUST

Abstract

The continuous scaling of integrated circuit technology is challenging the Cu interconnect’s physical limit. The resistivity of Cu increases rapidly due to the scattering leading to large signal transmission delay. The increasing current density makes Cu interconnect unreliable due to the electromigration. Carbon nanotube (CNT) is a promising candidate for vertical interconnect (vias) owing to its high current density capacity, electrical/thermal conductivity and high aspect ratio.
 
CMOS-compatible CNT synthesis approaches were developed on Ti silicide and Ni silicide substrates. A multilayer (Ni/Al/Ni) catalyst design was proposed to enhance nanoparticle formation by suppressing the diffusion of Ni into silicide and the sintering of Ni nanoparticles. Owing to the stable, high-density and evenly distributed nanoparticle catalysts with the multilayer catalyst design, we have synthesized vertically aligned multiwall CNTs (MWCNTs) with a wall density 5.2×1012/cm2. The proposed catalyst design enables CNT synthesis at a temperatures as low as 350°C. 
 
We developed a CNT via integration technology. To effectively preserve the surface properties of CNT tips and thus reduce the contact resistance of the CNT via, an integration process combining the selective CNT growth inside vias and the O2 plasma-assisted post-CNT treatment was explored. A low CNT via resistance of 1.08×10-6Ωcm2 was obtained by preserving CNT’s surface properties, enabling inner walls of MWCNT for parallel current conduction, and eliminating the side-wall CNT growth.
 
The scalability of the CNT via technology was studied through the fabrication of sub-100nm CNT vias on Ni silicide and the investigation on the scaling trend. The integration of submicron CNT vias with silicided Si transistor demonstrated the functionality of the transistor after the integration. The CMOS-compatible CNT via technology developed in this thesis is a step forward towards the application of CNT interconnect in CMOS technology.