Examination Committee

Prof Albert Chi Shing CHUNG, CSE/HKUST (Chairperson)
Prof Kevin CHEN, ECE/HKUST (Thesis Supervisor)
Prof Anthony H.W. CHOI, Department of Electrical and Electronic Engineering, The University of Hong Kong (External Examiner)
Prof Zhiyong FAN, ECE/HKUST
Prof Lining ZHANG, ECE/HKUST
Prof Lilong CAI, MAE/HKUST

Abstract

Power devices are key components to harness the use of electricity in power transmission, motor drives, DC-DC converters, etc. As silicon power devices are approaching their performance limits, wide-bandgap semiconductors (GaN and SiC) with superior material properties become critical to further enhancing the device performance and enabling new applications. Aiming at finding solutions to several critical challenges associated with the gate-controlled channel in GaN- and SiC-based power switching transistors, this thesis focuses on development of channel engineering techniques.

Firstly, an enhancement-mode (E-mode) GaN double-channel MOS-HEMT (DC-MOS-HEMT) is proposed to simultaneously obtain good threshold voltage (Vth) control and low channel resistance. Conventional single-channel MOS-HEMT with partially recessed gate faces difficulties in Vth control, while MOS-HEMT with fully recessed gate suffers from high MOS-channel resistance due to low channel mobility. The proposed DC-MOS-HEMT solves the dilemma by using two parallel channels. The gate recess is terminated at upper channel to control Vth, while the lower channel serves as a low-resistivity current path. The coupling strength between the two channels is identified as a critical design parameter, both experimentally and theoretically. The E-mode DC-MOS-HEMTs deliver robust Vth and high performance including a positive Vth of 1.4 V, a low Ron of 6.9 W/mm, a large breakdown voltage of 705 V, a steep SS of 72 mV/dec and robustness against process variation.

Secondly, a new SiC trench/planar MOSFET (TP-MOS) structure is proposed to increase channel density in vertical SiC power MOSFETs. The TP-MOS can achieve a lower Ron, a reduced electric-field in gate oxide and an enhanced switching performance. Furthermore, the termination of the critical p-shield structure in SiC trench MOSFET is systematically studied with numerical device simulation. A charge storage mechanism is found to be responsible for dynamic performance degradation in the floating p-shield configuration, suggesting the necessity of a grounded p-shield.

Finally, a GaN/SiC hybrid field effect transistor (HyFET) is proposed to take full advantage of GaN’s and SiC’s unique benefits. The GaN HEMT boasts high channel mobility, but is unsuitable for high voltage applications due to the lateral configuration. The vertical SiC MOSFET, however, suffers from low channel mobility. The proposed HyFET utilizes an AlGaN/GaN channel to reduce channel resistance and a vertical 4H-SiC drift region to sustain the high off-state voltage. Remarkable improvements on Ron, CGD, and gate charges are achieved in the HyFET.