MPhil in Electronic & Comp Engg - Floorplan-aware Design Space Exploration for High-level Synthesis Dataflow Designs on Multi-die FPGA

Name: MPhil in Electronic & Comp Engg - Floorplan-aware Design Space Exploration for High-level Synthesis Dataflow Designs on Multi-die FPGA
Start: 2022-08-09
End: 2022-08-09

2022 年 8 月 9 日

3:00pm - 6:00pm

, HKUST

Supporting the below United Nations Sustainable Development Goals:支持以下聯合國可持續發展目標：支持以下联合国可持续发展目标：

活动形式

论文答辩

候选人

DU, Linfeng

语言

英文