BEGIN:VCALENDAR
PRODID:-//HKUST Drupal Platform//EN
VERSION:2.0
BEGIN:VTIMEZONE
TZID:Asia/Hong_Kong
BEGIN:STANDARD
DTSTART:20071104T020000
TZOFFSETFROM:+0700
TZOFFSETTO:+0800
TZNAME:HKT
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP;TZID=Asia/Hong_Kong:20260513T025400
DTSTART;TZID=Asia/Hong_Kong:20220809T150000
DTEND;TZID=Asia/Hong_Kong:20220809T180000
LOCATION: , HKUST
SUMMARY:MPhil in Electronic & Comp Engg - Floorplan-aware Design Space Exploration for High-level Synthesis Dataflow Designs on Multi-die FPGA
UID:34759
END:VEVENT
END:VCALENDAR