Joint seminar by HKUST - ACE and EDSSC - Materials Innovation for Future Electronics

Internet of things demand large performance improvements in integrated circuit systems. Two possible approaches exist for advancing IC fabrication for future electronics. I would discuss on materials development associated with these two approaches.

(1) Continue the transistor scaling (Moore’s Law). With the scaling for future technology nodes, the gate controllability becomes weaker owing to the pronounced source-drain tunneling. Hence, the transistor body thickness needs to be reduced to ensure efficient electrostatic control. Thin materials with perfect surfaces such as transition metal dichalcogenide (TMD) monolayers offer a great chance to continue the scaling.[1] The growth of wafer-scale single-crystal 2D materials, including insulating hexagonal Boron Nitride (h-BN)[2] and semiconducting TMD[3-4], and the new metal contact [5] to 2D layers have thus become a central research topic in modern electronics.  

(2) Construct 3D integrated circuits with a monolithic approach.  Few examples include, adding sensor functionalities, constructing upper-layer logic circuits or memory devices on CMOS Si wafers, or stacking logic with memory devices.[6] Obviously, the research on materials and processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), is needed. Here, I like to use a case to illustrate the benefits of monolithic 3D integration, where we add carbon nanotube transistors on TSMC 28 nm CMOS technology wafers to save the footprint and power consumption. [7]

[1] M.-Y. Li et al. Nature 567, 169 (2019)  [2] T.-A. Chen et al. Nature 579, 219 (2020).  [3] Areej Aljarb et al. Nature Mater. 19, 1300 (2020) [4] M.-Y. Li et al. Science 349, 524 (2015) [5] P.J Shen et al, Nature (2021) [6] Deji Akinwande et al., Nature 573, 507 (2019) [7] C. C. Cheng et al. IEDM (2019)