Examination Committee

Prof James SHE, ECE/HKUST (Chairperson)
Prof Wei ZHANG, ECE/HKUST (Thesis Supervisor)
Prof Chi Ying TSUI, ECE/HKUST

Abstract

Big data analytics is a hot topic in academia and industry because of its diverse applications in many domains such as finance and security. However, scrutinizing the tremendous amount of data is far from the capabilities of mainstream computers. The programmable System-on-Chips (SoC) which accommodates the CPU cores and FPGA fabric on the same chip offers promising avenues in processing the huge data sets.

One of the challenges in exploiting the programmable SoC systems is delay overhead due to moving the data back and forth between CPU cores and FPGA fabric. The first part of this thesis studies the analytical performance model for transferring data stored in CPU side to FPGA side and vice versa through all different communication ports and data paths available in a typical programmable SoC.

In the second part of this thesis, we investigate the efficient methodology and designs for development of big data analytics by exploiting the Complex Event Processing in CPU/FPGA heterogeneous platforms. The existing hardware designs for this purpose all target the explicitly defined complex events, however, there are many scenarios that some of the events may not be explicitly known ahead of detection. In this thesis, we proposed a general complex event detection methodology which is capable to process the implicitly-defined events. The concepts of dynamic state machine, and context switching mechanism are introduced and an iterative and a parallel architecture based on the network of processing elements are proposed. The two proposed architectures were implemented on a typical CPU/FPGA heterogeneous architecture and evaluated against several synthetic data streams which prove their effectiveness according to each design objective.