ECE Seminar - 3D Integration Strategies for Organic Printed Electronics

Printed and flexible electronics face intrinsic limits when confined to planar device layouts. We present a unified strategy based on three-dimensional (3D) transistor integration and 3D channel engineering to overcome these constraints across logic, memory, sensing, and biointerfaces. Our fully inkjet-printed 3D complementary OFETs vertically stack p- and n-type transistors with a shared gate, achieving 100% yield, uniform operation, and functional logic including inverters, NAND gates, and full adders. Extending this concept, 3D monolithic dual-gate and triple-transistor structures on flexible substrates use sequentially printed metal and semiconductor layers to enhance transconductance, suppress partial depletion, and achieve record device density with year-long stability. This architecture enables 3D-stacked organic SRAM with the smallest cell size and highest static noise margin reported for printed organic memories. Finally, 3D multimodal sensor arrays and 3D electrolyte-surrounded OECTs exploit vertical stacking and micro/nanostructured channels to achieve independent tactile–thermal sensing and 26 kHz bandwidth. Collectively, these advances demonstrate that 3D integration fundamentally elevates the performance ceiling of printed electronics and establishes a scalable pathway toward next-generation intelligent, flexible systems.