Integrated circuits (IC) are the foundation stones of the modern information society. However, as the design complexity keeps increasing, the chip design cost is skyrocketing. Semiconductor companies are in increasingly greater demand for experienced man-power and stressed with unprecedented longer turnaround time. Therefore, there is a compelling need for essential improvements in design efficiency through new methodologies and design automation techniques. In this talk, I will present intelligent chip design and implementation techniques based on machine learning (ML) methods, whose major strength is to explore highly complex correlations based on prior data. These techniques cover various chip-design objectives, including power, timing, interconnect, IR drop, routability, and design flow quality. Instead of spending tremendous engineering effort in developing the customized ML model, I propose to automate the development procedure. More importantly, I target benefiting the whole chip life cycle with a unified ML framework for both chip design and runtime. This involves automatically designing a low-cost monitoring module as part of the circuit RTL. These ideas will be illustrated in detail with my recent works on circuit routability and power. Finally, I will share my concrete future research plans.