Real-Time Techniques and Low-Power Architecture Design for Video Coding
3pm
Room 2405 (Lifts 17-18), 2/F Academic Building, HKUST

Supporting the below United Nations Sustainable Development Goals:支持以下聯合國可持續發展目標:支持以下联合国可持续发展目标:

Examination Committee

Prof Qian LIU, IELM/HKUST (Chairperson)
Prof Chi Ying TSUI, ECE/HKUST (Thesis Supervisor)
Prof Daniel P K LUN, Department of Electronic and Information Engineering, The Hong Kong Polytechnic University (External Examiner)
Prof Roger S K CHENG, ECE/HKUST
Prof Weichuan YU, ECE/HKUST
Prof Long QUAN, CSE/HKUST 

 

Abstract

Video applications are widely adopted in a variety of fields, such as communication, entertainment, and surveillance. In the past decades, the demands for higher quality and higher resolution video content never cease. To efficiently transmit and store the huge video data, generations of video coding standards, such as H.264 and HEVC, have been proposed over the years. The coding efficiency has been improved significantly at the cost of tremendous complexity increase. It poses a challenge to the video coding implementation on portable devices with limited power. Low-complexity video coding technologies and low-power hardware architectures are therefore important. In this thesis, we tackle this problem at both algorithmic and architectural levels. We focus on the design of the most computational intensive module of video coding, the inter prediction, which includes the motion estimation and the mode decision. By using the statistical modeling of the motion data and thorough analysis of the prediction residual, a joint rate-complexity-distortion optimization framework is proposed and fast algorithms are developed to accelerate the prediction process. The coding complexity is optimized while maintaining the required coding performance. At the architectural level, a VLSI architecture is developed based on a novel way to calculate the sum of absolute difference (SAD) for the motion estimation algorithm, By re-using the calculation, the computation complexity and hence the power consumption are reduced. A low-power systolic processing elements array and an advanced memory hierarchy are designed, which allows a real-time processing of 8K resolution video with only half of the power consumption when compared with the state-of-the-art design.

Speakers / Performers:
Mr Luheng JIA
Language
English
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