Public Research Seminar by Microelectronics Thrust, Function Hub, HKUST (GZ)  - Silicon Photonic Connectivity for Efficient Neural Network Acceleration

Deep neural networks (DNNs) have achieved unprecedented success in a variety of applications. This success is from considerable demands for data and computations, which have spurred a pronounced interest in enhancing DNN acceleration through parallelism and specialization. At the core of any DNN accelerator lies the communication network, a pivotal component that connects the numerous processing units and orchestrates the intricate data movements resulting from the strategic arrangement of computations. As contemporary metallic-based interconnects encounter escalating limitations with the progression of system scaling, we consider silicon photonic interconnects a compelling alternative and investigate the consequent paradigm shift in communication network design and dataflow optimization.
This talk describes our reevaluation of DNN characteristics within the context of silicon photonics and three accelerator architectures that we have developed. The first architecture serves as a versatile platform for easy integration of existing chip-scale DNN accelerators while the inter-chiplet communication is supported by the adaptable silicon photonic interconnects. In the second architecture, silicon photonic interconnects are utilized to encompass both inter-chiplet and intra-chiplet communications, accompanied by a complementary dataflow that spatially distributes independent multiplications while iteratively performing accumulations. The third architecture facilitates multi-DNN execution through astute optimization of hardware resource allocation and one-hop communication support between arbitrarily partitioned hardware resources.