Examination Committee

Prof Kani CHEN, MATH/HKUST (Chairperson)
Prof George YUAN, ECE/HKUST (Thesis Supervisor)
Prof Ngai WONG, Department of Electrical and Electronic Engineering, The University of Hong Kong (External Examiner)
Prof Chi Ying TSUI, ECE/HKUST
Prof Andrew POON, ECE/HKUST
Prof Kai TANG, MAE/HKUST

Abstract

In recent years, the increasing demand on ultra-high-definition CMOS image sensor (UHD-CIS) and on the higher and higher image quality of the UHD-CIS is the result of the expanding application areas such as driver assistance system, smartphone, robot guidance and security surveillance. The resolution of the latest UHD-CIS increased to 33M pixels for 8K video quality. The UHD-CIS can generate a signal stream more than a Giga-bit per second (Gb/s). Therefore, UHD-CIS systems request high speed data links in both chip-to-chip (C2C) and device-to-device (D2D) communication interfaces. In this thesis, an optical wireless communication receiver and a digital clock and data recovery circuit for high throughput sensory applications are developed.

A 1 – 8 Gb/s optical wireless communication (OWC) receiver with a configurable transimpedance amplifier (TIA) is designed in a 65 nm CMOS process. The configurable TIA has two operation modes to accommodate optical wireless environment. The TIA in high-sensitivity mode (HSS) is designed for long distance data transmission whereas the TIA in high-speed data mode (HSD) mode is for short range high speed communication. A noise optimization technique for the TIA is presented in this thesis. The noise power can be minimized by maximizing feedback resistor and amplifier gain with optimized damping factor. The noise performance of the noise optimized TIA is theoretically three times smaller than a conventional 1st order TIA at very high data rate. Due to the increasing of the feedback resistor noise contribution at low data rate, the noise performance will get even better using the proposed noise optimization technique. The OWC receiver achieves 60 nArms input current noises at 1 Gb/s in HSS mode and 0.9 μArms input current noise at 8 Gb/s in HSD mode.

A clock data recovery (CDR) fabricated in 65 nm CMOS process is designed for high throughput sensory applications. It is a 2 – 8 Gb/s half-rate phase interpolator based digital CDR with phase selection technique. The phase selection technique accelerates the phase acquisition by limiting the maximum phase error. The phase acquisition is four time faster than a conventional phase interpolator based CDR. The designed CDR can achieve zero bit error during phase acquisition period, so no training bit sequence is required before valid data transmission. Therefore, the CDR allows burst operation and is ready for multiple-channel applications. The jitter of recovered clock is 6.8 psrms at 2 Gb/s and 3 psrms at 8 Gb/s.