Examination Committee

Prof David Karl BANFIELD, LIFS/HKUST (Chairperson)
Prof Philip MOK, ECE/HKUST (Thesis Supervisor)
Prof Kong-Pang PUN, Department of Electronic Engineering, The Chinese University of Hong Kong (External Examiner)
Prof Wing Hung KI, ECE/HKUST
Prof George YUAN, ECE/HKUST
Prof Yi-Kuen LEE, MAE/HKUST

Abstract

Radio-frequency (RF) power amplifiers (PA) are top power consuming components, especially with today’s 4G communication enabled by long term evolution (LTE) technology. To improve the PA’s efficiency, dynamic power supply technologies, such as average power tracking (APT), envelope tracking (ET) and envelope elimination and restoration (EER) have been proposed. In APT systems, the supply modulator adjusts the supply voltage according to the average power of the signal, similar to fast-dynamic-voltage-scaling (DVS) for digital circuits. For ET and EER, the supply modulator tracks the instantaneous changes in the envelope, thus the bandwidth of the tracking signal increases significantly. ET and EER supply modulators usually adopt a hybrid topology of a switching amplifier assisted by a linear amplifier to tradeoff between efficiency and bandwidth. High-frequency 3-level switching converters are good candidates for the APT application and very suitable to be the switching amplifier in the hybrid topology due to the advantages of high efficiency, small ripple and fast tracking speed.

To designing robust and fast integrated 3-level buck converters, a systematically analysis is conducted. Design considerations for real circuitry implementations, and the non-idealities’ influences on the voltage across the flying capacitor and the power efficiency are discussed. The loop-gain function with non-idealities is derived and verified with simulation and measurement results.

After the systematic analysis, a 50-MHz 5-V-input 3-W-output 3-level buck converter prototype is presented. A real-time flying capacitor (CF) calibration is proposed to ensure a constant voltage of Vg/2 across CF, which is highly dependent on various practical conditions. The calibration is essential to ensure the reliability and minimize the inductor current and output voltage ripple. In the measurement, the voltage across CF is always calibrated to Vg/2 under various conditions to release the voltage stress on the power transistors and CF, and to ensure reliability with up to 69% output voltage ripple reduction. A 90% peak efficiency and a 23–29 ns/V reference tracking response are also observed.

With the successful implementation of the 3-level buck converter, an AC-coupling supply modulator of a 25-MHz 3-level switching amplifier assisted by a wide-bandwidth linear amplifier is implemented for a fully-integrated CMOS PA for LTE applications. A multi-loop control is designed to fasten the switching amplifier speed, thus improving the overall efficiency. A high-frequency path is proposed to extend the bandwidth of the supply modulator from 33.9 MHz to 69.2 MHz without additional current consumption. The supply modulator measures 88.7% efficiency tracking a LTE-20MHz 16-QAM envelope. The multi-loop control improves the efficiency by up to 4%.