Examination Committee

Prof Philip K T MOK, ECE/HKUST (Chairperson)
Prof Howard LUONG, ECE/HKUST (Thesis Supervisor)
Prof George Jie YUAN, ECE/HKUST

Abstract

Demands for low-cost portable devices with high data rates have been continuously grown. To achieve high data rates, spectrally-efficient complex modulation schemes, like 64-QAM, are employed in modern wireless communication systems such as long-term evolution (LTE). Many systems-on-chip have been successfully demonstrated in low-cost CMOS technologies, integrating almost all critical blocks, including low-noise amplifiers, mixers, filters, frequency synthesizers, data converters, and digital baseband processors. However, many design challenges remain for designing and integrating CMOS power amplifiers (PAs) with high performance in terms of output power, power efficiency, and linearity.  First, high peak-to-average power ratio (PAPR) requirement leads to lower PA efficiency.  Second, CMOS technology is not a good choice for PA implementation due to its low breakdown voltage and lossy substrate.

In this thesis, an efficient CMOS Envelope-Shaping-and-Tracking (EST) power amplifier system for LTE applications is proposed, integrating a high-efficiency wide-band CMOS supply modulator (SM) and a fully-integrated high-power CMOS hybrid class-E PA. In particular, the proposed envelop shaping reduces the burden of SM in conventional Envelope-Elimination-and-Restoration (EER) architecture, and the mode-switching PA makes full use of the switching PA’s linear region to reduce signal distortion at low output power level. The CMOS PA achieves 28dBm output power with 43.5% efficiency.

Fabricated in a 65-nm CMOS process, the whole EST system measures 35.7% efficiency, and -32.1dBc E-ACLR at an average output power of 23.9dBm under 2.4V system supply voltage for a 20MHz BW 16-QAM LTE signal without using any digital pre-distortion.