Rational design of gate for steep-slope MoS2 transistors
The ever-decreasing size of transistors requires effectively electrostatic control over ultra-thin semiconductor body. Rational design of the gate configuration can fully persevere the intrinsic property of two-dimensional (2D) semiconductors. Here we design and demonstrate MoS2 transistors with omega-shaped gate, in which the local gate coupling is enhanced by the non-planar geometry. The omega-shaped non-planar transistors exhibit a high current of 0.89 A/μm. Scaling down the dielectric while maintaining high quality on 2D semiconductors remains challenging. A 4.5 Å van der Waals (vdW) gap is formed between dielectric and channel, which is enabled by the supersaturated oxygen concentration in the dielectric formation process. The MoS2 vdW-gap-gated transistors present a negligible hysteresis of 10 mV with ideal steep subthreshold slope of 62 mV/dec, very close to the physical limit of 60 mV/dec. Moreover, to break the fundamental Boltzmann limitation for power-efficient operation, MoS2 negative-capacitance field-effect transistors (NC-FETs) are constructed with self-aligned top-gated geometry and demonstrate steep subthreshold swing (SS) of 42.5 mV/dec. Finally, we perform an ultra-steep SS value below 1 mV/dec in the resistive-gated MoS2. The strategies present here is feasible to reach an optimum balance between high performance and low power consumption in future advanced electronics.
Prof. Liao is the Professor in Hunan University, and he has carried out the studies on the heterogeneous integration and device architecture based on 2D semiconductors systematically. To achieve high-performance field effect transistors, he focuses on surface and interface engineering, employs van der Waals heterogeneous integration and ultrathin buffer layer methods, and integrates gate dielectrics and metal electrodes on the surface of 2D semiconductors. The results effectively suppress the defects of 2D semiconductors caused by traditional deposition techniques, reduce the defect density at gate dielectric/2D semiconductor interface, weaken the pinning effect between metal electrode and 2D semiconductor, and finally obtain high quality device interface. Additionally, he also develops the surface modification and interlayer embedding technology, which are employed to achieve layers-independent physical properties in 2D superlattice structures. So far, he has published more than 200 papers in SCI journals, including Nature, Nature Electron., Nature Commun., Nano Lett., and Adv. Mater., and so on. Meanwhile, all these papers have been cited more than 17000 times by others, and the corresponding H factor is 77.