Examination Committee

Prof Jiheng ZHANG, IELM/HKUST (Chairperson)
Prof George YUAN, ECE/HKUST (Thesis Supervisor)
Prof Ngai WONG, Department of Electrical and Electronic Engineering, The University of Hong Kong (External Examiner)
Prof Chi Ying TSUI, ECE/HKUST
Prof Ross MURCH, ECE/HKUST
Prof Gang WANG, CIVL/HKUST

Abstract

The high-speed high-precision analog-to-digital converters (ADC) are widely used in the field of image processing, information storage and wireless communication. To achieve high speed and high precision, relative to other structures, pipeline architecture ADC has its own advantage: it can take both accuracy and speed into account. With the continuous improvement of the process, the speed limit of the circuit is getting higher and higher, but at the meantime, the process dimension is going smaller and smaller with the supply voltage becoming lower and lower, which makes harder for the op-amp to achieve high gain. What’s more, the power consumption is usually very large because there are many stages in a pipelined-ADC and a power hungry op-amp is needed in each stage. So pipelined-SAR ADC is introduced to solve these problems.

Use a SAR ADC as the sub-ADC in the pipelined ADC instead of flash ADC could reduce the system complexity a lot. As my PhD research, I designed a pipelined-SAR with open-loop MDAC. To achieve high speed, an open-loop low gain and high bandwidth op-amp is used in MDAC. The power hungry high gain high bandwidth amplifier is cancelled to save the power. The gain is calibrated foreground using some parasitic capacitors array at the MDAC input. To push the sampling speed even higher, separated digital-to-analog (DAC) arrays are used for MDAC and sub-ADC to reduce the first stage SAR ADC bit-cycling time constant in order to compress the quantization time. A loop-unrolled asynchronous SAR ADC is used to speed up the sub-ADC further. This architecture uses n comparators for n-bit ADC. The outputs of the comparators could be directly given to the SAR DAC array without any extra logic and there is also no need for the comparators to do the reset within one conversion periods. In this way the SAR logic delay is cancelled. The comparators offsets need calibration. The offsets value would vary with the input common mode voltage, so background calibration is used to calibrate the offsets at the corresponding common mode voltage.

In this thesis, a 12-bit 400MS/s single channel pipelined-SAR ADC is implemented using UMC 65 nm CMOS process with 1.3V supply voltage. The chip includes the reference buffer, low jitter clock receiver and the LVDS output driver. Large decoupling capacitors are used in the ADC chip. The total area of the chip including the pads is 1.875x1.875mm2 with a core area of 0.5 x 1.1mm2. The measurement results show that the ADC core consumes 33mW power and the sampling speed can just achieve 300MS/s due to the parasitic. After the foreground gain calibration, the SNDR is 58.99dB and the SFDR is 72.77dB for 2MHz input. The design achieve a FoM of 152fJ/Conv-step.