ECE Departmental Seminar - High-Performance Computing-In-Memory Chiplet-based Artificial Intelligence Processor

With the development of Large Language Models (LLM), Artificial Intelligence (AI) has transitioned to the Mosaic moment for a new era. LLM's extensive parameters and multi-task learning capabilities enable it to handle complex and general AI tasks like intelligent assistants, content generation, and sentiment analysis. High-performance AI chips are in high demand to deploy LLM inference and drive further AI development. Chip performance is determined by three elements: computation efficiency, transistor density, and chip area. However, chip fabrication faces the "Technology Wall" due to physical limitations, especially when scaling under 5nm to achieve higher transistor density. Therefore, we must explore opportunities from the other two elements. Computing-In-Memory (CIM) is a promising architecture that overcomes the "Memory Wall" caused by LLM's large-scale parameters. Advanced chiplet integration offers an important solution to break the "Area Wall" by integrating multiple chiplets into a single package. In this talk, we will discuss how architecture innovation with CIM and advanced integration with chiplets can bring a new vision to designing high-performance AI processors for LLM acceleration. By leveraging these innovative approaches, we can overcome the limitations of traditional chip design and unlock the full potential of LLM in AI development.