Examination Committee

Prof Kai CHEN, CSE/HKUST (Chairperson)
Prof Chi Ying TSUI, ECE/HKUST (Thesis Supervisor)
Prof Chiu Sing CHOY, Department of Electronic Engineering, The Chinese University of Hong Kong (External Examiner)
Prof Roger CHENG, ECE/HKUST
Prof Wei ZHANG, ECE/HKUST
Prof Raymond WONG, CSE/HKUST
 

Abstract

5G communication is aiming for the connection of billions of devices with demanding throughput and latency requirement. Two of the key enabling technologies for the 5G wireless era are massive multiple-input multiple-output (MIMO) systems and capacity achieving polar codes. Excellent spectral efficiency and superior energy efficiency are the desirable benefits offered by massive MIMO. An efficient linear pre-coding scheme at the transmitter side is of paramount importance to enjoy the benefits of massive MIMO. In this work, we present a high-throughput and low-latency matrix inversion design for linear pre-coders deployed in massive MIMO systems. 
 
Polar codes are capacity achieving codes, which makes them a promising candidate for 5G. Successive cancellation decoding (SCD) and belief propagation decoding (BPD) are two common approaches for decoding polar codes. SCD is sequential in nature, while BPD can operate in parallel. Hence BPD is more attractive for low latency applications. However, due to the iterative nature of BPD, the required latency and energy dissipation increases linearly with the number of iterations. In this work, we present a novel scheme to reduce energy dissipation as well as decoding latency in BPD. Moreover, a high-throughput and energy-efficient VLSI architecture for the proposed low-complexity BPD is developed. A decoding throughput of 13.9 Gbps is achieved, along with a 60 ~ 73% improvement in energy efficiency and a 2x increase in hardware efficiency when compared with existing BPD implementations.
 
Finally, a novel concatenated low density parity check (LDPC) Polar code, in which a small outer LDPC code is concatenated with a larger inner polar code, is presented to improve the error correction performance of BPD. The proposed scheme results in 0.5dB performance improvement over SCD. Moreover, an energy efficient VLSI architecture for the proposed concatenated LDPC-Polar code is also developed, and implementation results are presented.