Department of Electronic and Computer Engineering Seminar - Low-Phase-Noise mm-Wave Oscillator and PLL for High-Speed Communications

High-speed wireless and wireline communication systems demand high-frequency local oscillator (LO) or clock signal with a sub-100fs jitter. This talk will introduce circuit techniques that enable power-efficient mm-Wave frequency synthesis. Firstly, the multi-core oscillator will be reviewed, which provides an effective way to reduce the phase noise in ultra-scaled CMOS technologies. Then, the multi-path synchronization techniques that reduce the phase noise penalty due to the frequency mismatch between multiple oscillator cores will be presented. Their effectiveness is demonstrated through a 26GHz quad-core oscillator and a 60GHz 16-core oscillator, which achieve best-in-class FoM@10MHz of 193.3 and 190.9 dBc/Hz, respectively. At mm-Wave frequency, the subsampling PLL (SSPLL) benefiting from a low inband phase noise is a promising candidate for low-jitter frequency synthesis. However, the SSPLL suffers from an inferior reference spur and limited locking time. The second part of this talk will focus on designing SSPLL to simultaneously achieve low jitter, reference spur, and fast locking time. Using the proposed function-reused VCO buffer and low-power fast frequency-locked loop, the 23.2-to-26GHz SSPLL prototype can achieve 48.3fs RMS jitter, −253.5dB jitter FoM, and 0.55µs-locking-time.