Examination Committee

Prof Howard LUONG, ECE/HKUST (Chairperson)
Prof Wing Hung KI, ECE/HKUST (Thesis Supervisor)
Prof George YUAN, ECE/HKUST

Abstract

On-chip spatial temperature sensors are used to perform hotspot detection at different locations of high-speed multi-core CPUs. Each spatial sensor is placed at a different location so that the local temperature information can be digitized and fed back to the thermal management unit. Tasks of the CPU can be assigned according to the local thermal budget of each core. The total number of hotspots can be reduced and thermal related faults can be prevented. The total number of high-power consumption sites is directly proportional to the clock speed and the total number and the complexity of the CPU cores. Compact on-chip spatial temperature sensor should be designed so as to minimize the cost of the high performance multi-core CPU.

There are two types of on-chip temperature sensing. The first one is for hotspot detection to signal a thermal fault of a particular CPU core, and an area-efficient low-resolution temperature sensor is needed. The other one is for high-resolution temperature sensing, and a more sophisticated temperature transducer and SD-based readout electronics is needed. There is tradeoff between the area budget and the temperature resolution requirements. In this thesis, an on-chip spatial temperature sensor with the first order SD-based readout electronics is designed and implemented. Experimental results show that it could satisfy the performance requirement of hotspot detection. Finally, under same hardware, a new sensor architecture is proposed with the aim of achieving high-resolution temperature sensing.