Department of Electronic and Computer Engineering Seminar - Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware

Today’s AI computing systems must handle both the explosions of input data and output solutions. Toward a greener and smarter society in the near future, those explosions must be processed with as low energy as possible while keeping the versatility of the information systems. Hence reconfigurable, low-bitwidth, and massively parallel computing architectures are getting more critical as they represent the best strategy to reduce both the memory usage and computation energy at once for a variety of applications. The talk will examine algorithm-level, architecture-level, and real-chip-level topics explored in the design efforts belonging to that architectural category. Hardware-software co-optimization examples embedded in these design showcases will be a key takeaway of the talk.