Thesis Examination Committee

Prof Yongli MI, CBE/HKUST (Chairperson)
Prof Johnny Kin On SIN, ECE/HKUST (Thesis Supervisor)
Prof T. Paul CHOW, The Electrical, Systems and Computer Engineering Department, Rensselaer Polytechnic Institute (External Examiner)
Prof Kei May LAU, ECE/HKUST
Prof Kevin Jing CHEN, ECE/HKUST
Prof Lilong CAI, MAE/HKUST

Abstract

GaN-based power devices are becoming promising candidates for power electronic applications, which benefits from the superior material properties of GaN compared with those of Si. A Si-GaN cascode configuration is widely adopted for practical use of GaN-based devices in power switching applications. However, this two-chip co-package approach introduces large interconnection parasitics (especially the parasitic inductance) during assembly. These large parasitics will cause undesirable ringing during fast switching, resulting in system instability and increased switching losses. One efficient way of minimizing parasitics is to monolithically integrate the Si and GaN-based devices on the same substrate with small interconnection distance. In doing so, the chip size and assembly costs can also be reduced. 
 
In this thesis, the process compatibilities, especially the influence of high-temperature treatment on AlGaN/GaN epitaxial layers, are first evaluated. The process module of growing AlGaN/GaN epitaxial structure in the recessed windows on the Si (111) substrate is developed. Second, a Si-GaN cascoded diode with a breakdown voltage of 557 V is experimentally demonstrated by using the proposed integration technology. The reverse recovery charge of the cascoded diode is 79 % less than that of the Si fast recovery diode. Furthermore, the switching characteristics of the monolithically integrated cascoded diode demonstrate the much less parasitic effects compared with the wire-bonded counterpart. Third, a Si-GaN cascoded field effect transistor is designed and experimentally demonstrated. The Si and GaN transistors are placed in a distance of 50 µm which is only 2.5 % of that of the conventional two-chip co-package approach (~ 2 mm). The fabricated cascoded FET features a threshold voltage of 3.2 V, a gate swing of 20 V, a specific on-resistance of 3.3 mΩ∙cm2 and a breakdown voltage of 696 V. It is shown that the Si-GaN monolithic cascoded FET is promising for the high-performance power switching applications.