MPhil in Electronic & Comp Engg - AI-Driven Middle-End Optimization in High-Level Synthesis for FPGAs

Name: MPhil in Electronic & Comp Engg - AI-Driven Middle-End Optimization in High-Level Synthesis for FPGAs
Start: 2025-08-08
End: 2025-08-08

8 August 2025

4:00pm - 7:00pm

Room 2408 (Lifts 17-18), 2/F Academic Building, HKUST

Supporting the below United Nations Sustainable Development Goals:支持以下聯合國可持續發展目標：支持以下联合国可持续发展目标：

Event Format

Thesis Defense

Candidate

GE, Jinming

Language

English