Examination Committee

Prof Kwok Yip SZETO, PHYS/HKUST (Chairperson)
Prof Jiang XU, ECE/HKUST (Thesis Supervisor)
Prof Andrew B KAHNG, Departments of Computer Science and Engineering, and Electrical and Computer Engineering, University of California (External Examiner)
Prof Tim CHENG, ECE/HKUST
Prof Chin-Tau LEA, ECE/HKUST
Prof Wei WANG, CSE/HKUST

Abstract

With the fast development of processor chips, power-efficient, high-bandwidth, and low-latency inter-chip interconnects become more and more important. Studies show that the bandwidth of traditional electrical interconnects will become bottlenecks in the near future. Optical interconnects promise high bandwidth, low latency, and could improve the chip pin performance for manycore processors. They are becoming potential alternatives for electrical interconnects. On the other hand, gaps between data rates of electrical interconnects and optical interconnects are continuously increasing. Electrical-optical (E-O) interface and optical-electrical (O-E) interface, which convert data between parallel electrical interconnects and serial optical interconnects, become more and more important. We systematically modelled optical and electrical interconnects in terms of crosstalk noises, attenuation, and receiver sensitivities. We modelled E-O and O-E interfaces in terms of energy efficiencies, areas and latencies. A new type of E-O and O-E interfaces, which serialize and deserialize data by optical weaving technologies, are proposed alongside. We developed a tool called optical and electrical interfaces and links (OEIL). The OEIL can be used to analyze the energy consumption, bandwidth density, area, and latency of electrical and optical interconnects, as well as the E-O and O-E interfaces. Furthermore, we propose an optical inter/intra-chip processor-memory communication network, called MOCA, which can significantly improve system performance and energy efficiency. We propose a method to optimize the floorplan of optical fat tree based network-on-chip, which can effectively reduce the number of crossings and minimize the interconnect length.