Examination Committee

Prof Roger S K CHENG, ECE/HKUST (Chairperson)
Prof Chi Ying TSUI, ECE/HKUST (Thesis Supervisor)
Prof Wai Ho MOW, ECE/HKUST
 

Abstract

Polar codes have attracted a lot of research interests recently due to their provably capacity-achieving performance. The decoders of polar codes include successive-cancellation (SCD) and list successive-cancellation decoder (LSCD). SCD performs well when decoding long code length but has large performance degradation in short-to-medium code length. LSCD is proposed to compensate SCD drawback. List size in LSCD directly determines LSCD performance. LSCD with large list size exceeds that of Turbo codes and Low-Density Parity-Check codes. However, large list size results in huge computation complexity and increasing latency and this limits the applicability of LSCD in low-latency or power-sensitive implementation. Therefore, low-latency and complexity design of LSCD are proposed in this thesis.

In low-latency design, latency optimizations are carried out at the system and algorithmic levels. In system level, selective expansion method is proposed such that some of the reliable bits are not expanded at the LSCD for reducing the latency. In the algorithmic level, a double thresholding scheme is proposed for a fast and good approximate-sort method for the list management operation in the LSCD to reduce the decoding latency for large list size. Experiments show that for list size of 16, the implementation achieves decoding throughput of 465Mbps by using UMC 90nm CMOS technology while the performance degradation comparing with the convention exact method is negligible.

In low-complexity design, the property of the relative path metric (RPM) of each list candidate with respect to that of the most-likely candidate is investigated. It is found that the correct candidate has a low possibility of having a large value of RPM and based on this property, a list pruning method and the corresponding low-complexity LSCDs are proposed. From the simulation results, as compared to the conventional LSCD, the proposed LSCDs have negligible performance loss while the computation complexity is reduced by more than 80%. In addition, the proposed design is hardware-friendly and easily adaptable to the existing LSCDs hardware architectures.