Examination Committee

Prof Roger S K CHENG, ECE/HKUST (Chairperson)
Prof Chi Ying TSUI, ECE/HKUST (Thesis Supervisor)
Prof Wei ZHANG, ECE/HKUST

Abstract

As the first class of forward error correction codes with provably capacity-achieving capacity, Polar Codes attract a lot of research interests recently. Short Polar Codes with Successive Cancellation Decoding (SCD) have moderate decoding latency and complexity. For better error performance, List Successive Cancellation Decoding (LSCD) has to be used, in which L candidate paths are kept. To implement LSCD, L decoding units are required to decode L paths in parallel and a list pruning mechanism is needed to select the L-best paths from the 2L paths generated from the L decoding units. To achieve a very low error correction performance, a large list size is needed and this increases the complexity and also the decoding latency of the LSCD. Special VLSI architectures are needed to optimize the complexity and latency.
 
In this thesis, we focus on the hardware implementation of SCD and LSCD for short Polar Codes. First, a high-throughput SCD architecture is proposed. To increase the decoding throughput, a hybrid decoder architecture is used, whose SCD calculations of the low stages are combined and Maximum-likelihood Detector is used to decode multiple bits at the same time. The throughput of such SCD for length 1K code can reach 1Gbps on FPGA implementation. Next, to reduce the latency of LSCD, algorithm and architecture co-optimization schemes are proposed. Efficient list management operation algorithms are developed to reduce the latency required for the sorting operation. Based on the low-latency algorithm, a high-throughput large list size LSCD architecture is proposed. Multi-bit decoding and look-ahead techniques are proposed to reduce the number of cycles required by the LSCD architecture. Experimental results based on ASIC implementation show that a 900Mbps throughput can be achieved for a 1K Polar code with a list size of 32. This throughput is much higher than the state-of-the-art implementation.