Examination Committee

Prof Ho Yi MAK, LIFS/HKUST (Chairperson)
Prof Kevin CHEN, ECE/HKUST (Thesis Supervisor)
Prof Jiyan DAI, Department of Applied Physics, The Hong Kong Polytechnic University (External Examiner)
Prof Andrew POON, ECE/HKUST
Prof Zhiyong FAN, ECE/HKUST
Prof Jiannong WANG, PHYS/HKUST

Abstract

GaN-on-Si lateral heterojunction power devices are currently being commercialized and used to implement power converters with impressive efficiency and compact size. The GaN power transistors with metal-insulator-semiconductor (MIS) gate structures, although being capable of offering the highly desired low gate leakage and large gate swing, have been hindered by obstacles in gate dielectric reliability and VTH (threshold voltage) instability. This thesis is devoted to developing device technology and physical understandings for high-performance GaN power MIS-HEMT and MIS-FET with high reliability and stability.

Firstly, SiNx deposited at 780 oC using LPCVD (low pressure chemical vapor deposition) was successfully implemented as a gate dielectric compatible with depletion-mode GaN MIS-HEMT. The LPCVD-SiNx exhibits the highest breakdown electric field of dielectric thin films on GaN to date. Gate leakage mechanisms are clarified with temperature-dependent characterization. Time-dependent dielectric breakdown (TDDB) measurement of the LPCVD-SiNx/GaN MIS-HEMT reveals promising lifetime of such devices in applications. Although the LPCVD-SiNx gate dielectric delivers superior performance, it cannot adequately suppress current collapse as a passivation layer. In the second part of this thesis, it is demonstrated that the effective AlN/SiNx passivation stack can sustain the high-temperature LPCVD-SiNx process, and thus is thermally compatible. The dynamic performance of LPCVD-SiNx MIS-HEMT is significantly improved with the AlN/SiNx passivation, especially under high drain bias switching with VDS > 100 V. 

To realize enhancement-mode (E-mode) GaN power device with LPCVD-SiNx gate dielectric and AlN/SiNx passivation, in the third part, we developed effective interface protection techniques to protect the etched-GaN surface in the high-temperature LPCVD process. Atomic-sharp interface can be obtained that eventually leads to E-mode LPCVD-SiNx/GaN MIS-FET with large positive VTH of +2.4 V and low on-resistance. In particular, TDDB reveals a 10-year lifetime for a forward gate bias of 11 V. Small recoverable positive and negative bias-temperature instabilities (PBTI and NBTI) were observed and the possible physical mechanisms origins were revealed.