Examination Committee

Prof Chi Wai HUI, CBME/HKUST (Chairperson)
Prof Hoi Sing KWOK, ECE/HKUST (Thesis Supervisor)
Prof Guglielmo FORTUNATO, Institute for Microelectronics and Microsystems, Consiglio Nazionale Delle Ricerche (External Examiner)
Prof Man WONG, ECE/HKUST
Prof Zhiyong FAN, ECE/HKUST
Prof Jiannong WANG, PHYS/HKUST

Abstract

This thesis focuses on small-grain poly-Si TFTs for high-resolution FPDs and SoP applications. Firstly, different kinds of treatments are applied to small-grain poly-Si TFTs to generate high-performance device characteristics. Then, the reliability of small-grain poly-Si TFTs is systematically characterized and studied. Last, self-aligned top-gate μc-Si TFTs are fabricated and investigated.

For the device performance improvement, three kinds of treatments are applied to small-grain poly-Si TFTs. By integrating a high-k gate dielectric with bridged-grain (BG) active channel, the small-grain poly-Si TFTs exhibit outstanding performance improvements, especially for off-state characteristics. The two-dimensional dot-array (DA) doping technology is invented to improve device performance. With the DA doping in the active channel, device characteristics show great improvements. A simple method is introduced to grow thermal SiO2 interlayer between small-grain poly-Si channel and the high-k gate dielectric for high-performance small-grain poly-Si TFT. The effect of the buffer layer, O2 annealing and the Si interstitials is clarified.

For the device reliability test, four kinds of stresses are performed. Firstly, environmental-stress-related parasitic effect in poly-Si TFTs is clarified, and a method is proposed to reduce such effect. Secondly, DC-stress-induced degradation in poly-Si TFTs is investigated. BG TFTs exhibit better HC reliability, SH reliability and NBTI reliability. Thirdly, AC-stress-induced degradation in poly-Si TFTs is performed. A physical non-equilibrium junction degradation model is proposed. Lastly, device degradation under “practical” stress is systematically studied in poly-Si TFTs. For both AC stress and “practical” stress, BG poly-Si TFTs shows better reliability.

For μc-Si TFTs, self-aligned top-gate μc-Si TFTs are fabricated and characterized. By replacing high-temperature SiO2 with low-temperature SiO2, the performance of μc-Si TFT could be greatly improved due to the prevention of hydrogen diffusion to the air. BG structure is also successfully applied to the self-aligned top-gate μc-Si TFTs. By employing the BG structure, the device performance is further improved.