Examination Committee

Prof Pak Wo LEUNG, PHYS/HKUST (Chairperson)
Prof Patrick YUE, ECE/HKUST (Thesis Supervisor)
Prof Jri LEE, Department of Electrical Engineering, National Taiwan University (External Examiner)
Prof Man Sun CHAN, ECE/HKUST
Prof Volkan KURSUN, ECE/HKUST
Prof Jinglei YANG, MAE/HKUST
 

Abstract

Due to the rapid growth of the data traffic and the integration density of systems, the electromagnetic compatibility (EMC) of communication circuits is increasingly challenging to accomplish. In modern data centers, thousands of paralleled backplane communication links enable the tremendous volume of data throughput. However, these backplane links also generate undesired electromagnetic interference (EMI), which can potentially cause system malfunction.
 
In a typical backplane communication link, differential non-return-to-zero (NRZ) signaling has been widely used for years. However, non-linear distortion of differential NRZ signals leads to a large common-mode (CM) noise at the double Nyquist frequency, which is a primary source of EMI. Therefore, the first half of the thesis focuses on investigating the CM noise of NRZ signals to understand the EMI issue in high-speed backplane links. Similar to the NRZ signaling, 4-level pulse amplitude modulation (PAM-4), which is the key solution for the next generation of 200/400 GbE communications, also suffers from the similar EMI problems. Hence, the second half of the thesis focuses on the EMI-related CM noise of PAM-4 signals.
 
In the first half, the analysis of EMI-related CM noise of differential NRZ signals is presented from a circuit design perspective. A current-mode logic (CML) driver circuit is used for analysis and simulations. It is observed that the CM noise is correlated with the data rate, amplitude, and mismatch of rising and falling edges. Accordingly, a method for EMI reduction is proposed by optimizing the signal swing and the biasing voltage of the circuit. The proposed method is experimentally verified on a test chip fabricated in a 65 nm CMOS process.
 
In the second half, the analysis of PAM-4 signals is presented, showing a correlation between the EMI-related CM noise and the system architecture. It is observed that the CM noise of a PAM-4 transmitter with a thermometer-coded architecture is intrinsically lower than the CM noise of a transmitter with a typical binary-scaled architecture. Hence, a mathematical expression is derived to estimate the CM noise of the PAM-4/8/16 signals, and transistor-level simulations in a 65 nm CMOS process are performed to further evaluate the correlation between the CM noise and the system architecture.