Department of Electronic & Computer Engineering - ECE Future Leaders PG Seminar Series
Session 1: Microsecond Fringe-field-free Continuous 2.25 𝛑 Phase Modulation Based upon Non-linear Kerr Effect of Vertical Aligned Deformed Helix Ferroelectric Liquid Crystal
Speaker: Miss. YUAN Zhengnan, PhD (ECE), HKUST
Here we disclose a fast (ON time ~50 μs and OFF time ~25 μs at 55℃ ), high-contrast, continuous phase modulator without fringe field effect (FFE). The phase modulator utilizes the Kerr effect of vertical aligned deformed helix ferroelectric liquid crystal (VADHFLC). Specifically, FFE is a long-term problem for nematic liquid crystal (NLC). In this article, we are disclosing, for the 1st -time found, that no FFE exists for VADHFLC, even for phase modulator with 1 μm pixel pitch, which is an attractive feature for ultra-high-resolution display and photonic applications. Moreover, the Kerr constant is 88 nm/V2, and the contrast ratio is larger than 1000:1. It is a promising candidate for high-PPI AR/VR displays, wavelength selective switch (WSS), hologram, adaptive optics, and LiDARs.
Session 2: High-Performance Analytical Mixed-size Placer for FPGA
Speaker: Mr. LIANG Tingyuan, PhD (ECE), HKUST
To enable the performance optimization of application mapping on modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous works of analytical placers.
In this work, we propose AMF-Placer, an open-source Analytical Mixed-size FPGA placer supporting mixed-size placement on FPGA, with an interface to Xilinx Vivado. To speed up the convergence and improve the quality of the placement, AMF-Placer is equipped with a series of new techniques for wirelength optimization, cell spreading, packing, and legalization. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that AMF-Placer can improve HPWL by 20.4%-89.3% and reduce runtime by 8.0%-84.2%, compared to the baseline. Furthermore, utilizing the parallelism of the proposed algorithms, with 8 threads, the placement procedure can be accelerated by 2.41x on average.
Miss. Zheng-Nan Yuan (SID Student Membership) was born in 1997. In 2018, she received her first-class honoured B.Eng and B, Sc from Glasgow College, UESTC. She is a PhD candidate supervised by Prof. Abhishek Kumar Srivastava at State Key Laboratory of Advanced Displays and Optoelectronics Technologies, Department of Electronics and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong since 2018. Her research field is mainly about ferroelectric liquid crystals for LiDAR applications (Received Distinguished Paper Award in PGWS 2021, HK); amplitude and phase modulation devices (Received Distinguished Student Paper Award in SID 2022, USA) based on fast liquid crystals. In 2021, she received the Academic Excellence Award for Continuing PhD Student, HKUST. Until now, she has published 37 papers, including 8 journals and holds 3 patents
Mr. Tangyuan Liang received his B.S degree in Electrical and Information Engineering from Zhejiang University, Hangzhou, China, in 2017. He is currently a Ph.D. student in the Department of Electronics and Computer Engineering, the Hong Kong University of Science and Technology, under the supervision of Professor Wei ZHANG. His current research interests include high-level synthesis, logic synthesis, FPGA placement, and computer architecture.