Department of Electronic and Computer Engineering Seminar - High-Performance PLLs: Evolution, Challenges, and Future Directions
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Phase-locked loop (PLL) is one of the key techniques for both communication and radar systems. Various functions in communication and radar systems, including clock generation, frequency synthesis, serial-to-parallel conversion, frequency and phase modulation, clock synchronization and distribution, coherent and non-coherent demodulation, clock and carrier recovery, directly or indirectly rely on PLLs. High performance PLL is one of the cutting-edge topics in the field of integrated circuit and system design. It involves various research directions such as mixed-signal circuit design, digital algorithms, and system-level architecture. This lecture will discuss the high-performance PLL circuit and architecture evolution, review the latest research progress and discuss the future development trends of high-performance PLLs.
Prof. Wei Deng is currently a tenured associate professor at Tsinghua University, Beijing, China. He received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan. He was with Apple Inc., Cupertino, CA, USA, working on RF, mm-wave, and mixed-signal IC design for wireless transceivers and Apple A-series processors. He has authored or co-authored over 160 IEEE journal and conference articles including 40+ ISSCC and JSSC. Dr. Deng currently serves as a Technical Program Committee Member for ISSCC, VLSI, CICC, A-SSCC, RFIC, and ESSCIRC. He is a Guest Editor and an Associate Editor of the IEEE SSC-L, a Guest Editor of the IEEE JSSC, and a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS).