Department of Electronic and Computer Engineering Seminar - Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware

10:00am - 11:30am
Rm 2405, 2/F (Lift 17, 18), Academic Building, HKUST

Today’s AI computing systems must handle both the explosions of input data and output solutions. Toward a greener and smarter society in the near future, those explosions must be processed with as low energy as possible while keeping the versatility of the information systems. Hence reconfigurable, low-bitwidth, and massively parallel computing architectures are getting more critical as they represent the best strategy to reduce both the memory usage and computation energy at once for a variety of applications. The talk will examine algorithm-level, architecture-level, and real-chip-level topics explored in the design efforts belonging to that architectural category. Hardware-software co-optimization examples embedded in these design showcases will be a key takeaway of the talk.

Event Format
Speakers / Performers:
Prof. Masato Motomura
Tokyo Institute of Technology

Masato Motomura graduated and received Ph.D. from Kyoto University. He was a researcher in NEC central research labs and was also a visiting researcher at MIT. Then he became a professor at Hokkaido University, and now he is at Tokyo Institute of Technology leading AI computing research unit. He is actively working on reconfigurable and parallel architectures for deep neural networks, machine learning, annealing machines, and intelligent computing in general. He has been awarded the IEEE JSSC Best Paper Award, the IPSJ Best Paper Award, the IEICE Achievement Award, IEEE Fellow, Ichimura Award, and Yamasaki Award.

Recommended For
Faculty and staff
PG students
Department of Electronic & Computer Engineering
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